AMD plans to release its 3rd Generation EPYC processors, codenamed Milan, sometimes in late 2020, so it is not surprising that virtually all of its partners are busy testing early samples of the CPUs.
With thousands of samples in the wild, leaks become almost inevitable, as seen this past weekend where some preliminary information about the upcoming CPUs got published.
AMD’s 3rd Generation EPYC processors are based on the Zen 3 microarchitecture and feature EPYC Rome-like nine-die MCM design. Meanwhile, the new Zen 3 Core Complex Dies (CCDs) are made using an improved version of TSMC’s 7 nm process technology. In total, the CPUs are set to offer up to 64 cores with SMT, 128 PCIe 4.0 lanes, and an eight-channel DDR4-3200 memory subsystem. The new processors continue to use AMD’s SP3 socket and feature a TDP of up to 225 W – 240 W.
As it turns out, AMD decided to alter internal arrangement of its CCDs with its Zen 3 cores. Previously, each CCD features two quad-core Core Complexes (CCXs) with 16 MB of L3 cache per CCX. With Zen 3, each CCX features eight cores and a unified ‘32+ MB’ L3 cache. Such a CCD design lowers internal latencies and promises to improve instructions per clock (IPC) performance.
(Image credit: AMD)
Reports have already emerged of one AMD partner currently testing three EPYC ‘Milan’ CPUs featuring 64 and 32 cores and marked as 100-000000114-07 (64 cores, 9-die MCM with 256 MB of L3), 100-000000114-09 (64 cores, 9-die MCM with 256 MB of L3), and 100-000000117-03 (32 cores, 5-die MCM with 128 MB of L3). All the processors are based on the early A0 stepping silicon.
AMD’s 64-core 100-000000114-09 processor features a 1.6 GHz base clock as well as a 3 GHz boost frequency, whereas the 32-core 100-000000117-03 CPU runs at 1.8 GHz base and 3 GHz boost clocks. By contrast, today’s EPYC 7002 ‘Rome’ chips operate at up to 2.6 GHz base and up to 3.4 GHz boost frequencies.
Typically, early versions of CPUs are not supposed to run at high clocks, so expect final AMD EPYC 7003 processors to feature higher frequencies. Meanwhile, 3 GHz for a 64-core MCM seems high enough for A0 silicon, so it is plausible to expect AMD’s 3rd Generation EPYC processors to feature rather high clocks.
Source: Igor’s Lab (via Tom’s Hardware)
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With thousands of samples in the wild, leaks become almost inevitable, as seen this past weekend where some preliminary information about the upcoming CPUs got published.
AMD’s 3rd Generation EPYC processors are based on the Zen 3 microarchitecture and feature EPYC Rome-like nine-die MCM design. Meanwhile, the new Zen 3 Core Complex Dies (CCDs) are made using an improved version of TSMC’s 7 nm process technology. In total, the CPUs are set to offer up to 64 cores with SMT, 128 PCIe 4.0 lanes, and an eight-channel DDR4-3200 memory subsystem. The new processors continue to use AMD’s SP3 socket and feature a TDP of up to 225 W – 240 W.
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As it turns out, AMD decided to alter internal arrangement of its CCDs with its Zen 3 cores. Previously, each CCD features two quad-core Core Complexes (CCXs) with 16 MB of L3 cache per CCX. With Zen 3, each CCX features eight cores and a unified ‘32+ MB’ L3 cache. Such a CCD design lowers internal latencies and promises to improve instructions per clock (IPC) performance.
(Image credit: AMD)
Reports have already emerged of one AMD partner currently testing three EPYC ‘Milan’ CPUs featuring 64 and 32 cores and marked as 100-000000114-07 (64 cores, 9-die MCM with 256 MB of L3), 100-000000114-09 (64 cores, 9-die MCM with 256 MB of L3), and 100-000000117-03 (32 cores, 5-die MCM with 128 MB of L3). All the processors are based on the early A0 stepping silicon.
AMD’s 64-core 100-000000114-09 processor features a 1.6 GHz base clock as well as a 3 GHz boost frequency, whereas the 32-core 100-000000117-03 CPU runs at 1.8 GHz base and 3 GHz boost clocks. By contrast, today’s EPYC 7002 ‘Rome’ chips operate at up to 2.6 GHz base and up to 3.4 GHz boost frequencies.
Typically, early versions of CPUs are not supposed to run at high clocks, so expect final AMD EPYC 7003 processors to feature higher frequencies. Meanwhile, 3 GHz for a 64-core MCM seems high enough for A0 silicon, so it is plausible to expect AMD’s 3rd Generation EPYC processors to feature rather high clocks.
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Source: Igor’s Lab (via Tom’s Hardware)
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